Graphene is a single planar sheet of sp3-bonded carbon atoms that are densely packed in a honeycomb crystal lattice and which was first isolated in 2004. The carbon-carbon bond length in graphene is approximately 1.42 Å. Since the experimental verification the following year of many of its theoretically predicted electronic properties, single- and few-layer graphene has been suggested as a promising candidate material for future microelectronic devices. Graphene is in many respects similar to carbon nanotubes, but expectations are that for various applications graphene will be easier to control. This is partly because it can be patterned into arbitrary shapes by lithographic means which readily provides a degree of control difficult to achieve with nanotubes.
Nevertheless, smaller devices require not only novel materials but also a means of shaping those materials into a tiny circuit. State of the art, resist based, electron beam lithography (EBL) methods, notwithstanding throughput issues, rarely achieve a half-pitch of less than 20 nm on bulk substrates. Smaller features, if created by EBL, are in most cases of a special shape, e.g., an isolated line. It has been argued that resist-based EBL on a substrate is inherently limited to around 20 nm half-pitch for periodic patterns. Although electron beams can be focused to sub-angstrom diameters, scattered and secondary electrons generated in a bulk substrate and resist limit the modulation in the energy profile that can ultimately realized. Accordingly, the smallest feature sizes using EBL having not improved significantly over the last three decades.
On bulk substrate, the spatial resolution of electron-beam induced deposition (EBID) and also of convention lithography is limited by scattered and secondary electrons, with a minimum half pitch of around 20 nm. Good resolution has been achieved by EBID on ultrathin amorphous carbon and silicon nitride membranes (see, e.g., van Dorp, W. F., et al., One nanometer structure fabrication using electron beam induced deposition, Microelectronic Eng., 83, 1468-1470 (2006)).
An existing technique for producing a suspended graphene membrane is taught in Meyer, J. C., et al., The structure of suspended graphene sheets, Nature, 446, 60-63 and in the supplementary information to this publication (doi: 10.1038/nature05545). In this technique, graphene flakes are placed on an oxidized surface of a silicon wafer upon which a metal grid is produced by deposition of a metal, electron beam lithography, and etching.
Graphene holds potential for novel electronic, thermal and mechanical devices. Many devices currently made use graphene adhered to a substrate. However, for many potential applications, a suspended membrane of graphene is essential, such as for nanoelectromechanical devices. While there is the existing technique for producing suspended graphene that is discussed above, it is complicated and consequently expensive. A more efficient and less expensive technique is desirable. Further, graphene is useful for many devices as it has a high conductivity and is sensitive to “gating”. However, a new form of lithography is needed to make extremely small devices on graphene.